Three dimensional semiconductor integrated circuit having gate pick-up line and method of manufacturing the same

摘要

A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.

主权项

1. A semiconductor integrated circuit comprising:
a semiconductor substrate having a cell array region and a gate pick-up region, which include a plurality of pillars, respectively; buffer layers formed on the respective pillars included in the gate pick-up region; first gates formed on an outer circumference of the respective pillars included in the cell array region; second gates each surrounding an outer circumference of the corresponding pillar and the corresponding buffer layer included in the gate pick-up region; and a gate pick-up line electrically coupled to the second gates.