PHOTOREPEATED INTEGRATED CIRCUIT WITH COMPENSATION OF THE PROPAGATION DELAYS OF SIGNALS, NOTABLY OF CLOCK SIGNALS

摘要

Integrated circuits of large size produced by photorepetition of several mutually identical partial patterns are provided, more precisely to the compensation of propagation delays of signals (notably of clock signals) from one partial circuit to the following whereas the signals concerned must reach the various partial circuits simultaneously for proper operation of the whole. The compensation circuit provided in each partial circuit comprises a main transmission line for a master clock signal and a compensation line with multiple outputs, as well as a multiplexer for selecting one of the outputs, the output selected being different in the various partial circuits. The multiplexer provides a local clock signal in each partial circuit and these clock signals are synchronous despite the propagation delays.

主权项

1. An integrated circuit comprising N adjacent patterns, all identical, corresponding to N adjacent identical partial circuits of rank i=1 to i=N in the order of geographical succession of the partial circuits, each partial circuit comprising a main conducting line connected in cascade to the main conducting lines of the partial circuits of immediately preceding and immediately following rank, so as to allow the transmission in cascade of a master signal received on the partial circuit of rank 1, each main line introducing a propagation delay of duration T between an input of the main line and an output of the main line linked to a main line input of the circuit of immediately following rank, the integrated circuit comprising in each partial circuit of rank i:
a compensation conducting line with N successive outputs of rank i=1 to N, linked to the main line and establishing a propagation delay of duration T between the successive outputs, a multiplexer with N inputs linked respectively to each of the N outputs of the compensation conducting line, and control lines of the multiplexer, which are designed to select the multiplexer's input of rank i, linked to the output of rank N−i+1 from among the N outputs of the compensation conducting line,the output of the multiplexer of the partial circuit of rank i thus providing a local signal for this partial circuit.