FinFET DEVICE WITH ABRUPT JUNCTIONS

摘要

A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

主权项

1. A FinFET device comprising:
a plurality of semiconductor fin portions located on a plurality of pedestal insulator portions of an insulator layer, wherein each semiconductor fin portion of the plurality of semiconductor portions is located directly on and above one of the pedestal insulator portions of the plurality of pedestal insulator portion; a plurality of functional gate structures orientated perpendicular to and straddling each semiconductor fin portion; a dielectric spacer located on vertical sidewalls of each functional gate structure, wherein each dielectric spacer has outer sidewalls that are vertical coincident to vertical sidewalls of each semiconductor fin portion and vertical sidewalls of each pedestal insulator portion; a source-side doped semiconductor material portion located on one of said vertical sidewalls of each semiconductor fin portion and on one side of each functional gate structure; a drain-side doped semiconductor portion located on another of said vertical sidewalls of each semiconductor fin and on another side of each gate structure; a source region located in each semiconductor fin portion and along said one vertical sidewall of each semiconductor fin portion; and a drain region located in each semiconductor fin portion and along said another vertical sidewall of each semiconductor fin portion.