| 主权项 |
1. A stack type memory device, comprising:
a semiconductor substrate; a first stack structure and a second stack structure, each of the first and second stack structures including a plurality of memory cells stacked on the semiconductor substrate, wherein the first stack structure and the second stack structure are divided by an insulating plug; a plurality of bit lines formed at one side of the plurality of memory cells of the first and second stack structures, respectively, and stacked on the semiconductor substrate; and a plurality of word line structures, each of the word line structures including:
a gate insulating layer formed over the plurality of memory cells,first and second gate electrodes, wherein each of the first and second gate electrodes has a U-shape and directly contact the gate insulating layer, wherein the U-shape is formed of a first portion for covering a front side of each of the corresponding memory cells of the first or second stack structures, a second portion for covering a back side of each of the corresponding memory cells of the first or second stack structures and a third portion for covering a top side of the corresponding memory cell of the first and second stack structures, wherein the gate insulating layer is interposed between the first and second gate electrodes and the corresponding memory cells of the first and second stack structures, and the first to third portions are electrically connected with one another,a word line formed on the stack structures and the plurality of bit lines, wherein the word line is configured to select one of the gate electrodes of the plurality of word lines, andan interconnection unit electrically connected between the third portion of the gate electrode and the word line, wherein the plurality of memory cells constituting the first and second stack structures are connected in parallel. |
