| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control device for reducing the capacity of a secondary cache while maintaining latency reduction by the secondary cache.SOLUTION: When a cache mistake occurs in a first memory in response to a first access request from a first CPU core, and a cache hit is detected in a third memory 23, a part of data are read from a third memory and set as first leading data, and the residual data are read from a fourth memory 26 and set as first subsequent data of the first leading data as a response. When a cache mistake occurs in a second memory in response to a second access request from a second CPU core following the first access request, and a cache hit is detected in the third memory, a part of data are read from the third memory and set as second leading data, and the residual data are read from a fourth memory and set as second subsequent data of the second leading data as a response, and while the first subsequent data are read from the fourth memory, the second leading data are read from the third memory. |
