发明名称 LOW LATENCY COMPUTER SYSTEM POWER REDUCTION
摘要 Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.
申请公布号 US2015378425(A1) 申请公布日期 2015.12.31
申请号 US201414318342 申请日期 2014.06.27
申请人 Microsoft Corporation 发明人 Kelly Bryan D.;Khessib Badriddine;Govindan Sriram
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
主权项 1. A method of managing power in a multi-server computing system, the method comprising: detecting an occurrence of a current exceeding a threshold in a circuit that supplies power to multiple computing modules of the multi-server system; and in response to detecting the occurrence, reducing power consumption of at least two computing modules of the multiple computing modules, wherein reducing the power consumption for each of the at least two computing modules includes: asserting a speed reduction pin of a processor of that computing module;while the speed reduction pin of the processor is asserted, writing a speed control register of the processor of that computing module; andreleasing the speed reduction pin of the processor of that computing module.
地址 Redmond WA US