System and Method for Concurrently Checking Availability of Data in Extending Memories

摘要

A memory system for use in a system-in-package device (SiP) is disclosed. The memory system includes two cache memories. The first cache memory is on a first die of the SiP and the second cache memory is on a second die of the SiP. Both cache memories include tag random access memories (RAMs) corresponding to data stored in the corresponding cache memories. The second cache memory is of a different cache level from the first cache memories. Also, the first cache memory is on a first die of the SiP, and the second cache memory includes a first portion on the first die of the SiP, and a second portion on a second die of the SiP. Both cache memories can be checked concurrently for data availability by a single physical address.

主权项

1. A memory system for use in a system-in-package device (SiP), the system comprising:
a first 2-set cache memory of a first Level on a first die of the SiP, the first cache memory including a first tag random access memory (RAM) with a tag RAM array for each set, for storing one or more tags corresponding to data stored in the corresponding sets of the first cache memory; a second 2-set cache memory of a second Level different from the first Level, the second cache memory including a first portion on the first die of the SiP, and a second portion on a second die of the SiP, the second cache memory including a second tag RAM with a tag RAM array for each set, for storing one or more tags corresponding to data stored in the corresponding sets of the second cache memory; and a control logic circuit coupled to the first and second cache memories and configured to control a multiplexer for outputting data from either of the cache memories; wherein the first and second cache memories are coupled to a single physical address, and wherein a first set of tag bits and index bits of the physical address provided to the first tag RAM of the first cache memory is different from a second set of tag bits and index bits provided to the second tag RAM of the second cache memory, such that both cache memories can be checked concurrently for data availability by the single physical address.