| 摘要 |
<p>An FFT computing apparatus and method for suppressing area overhead of a circuit and increase in delay time for computing received signal power. A multiplier included in a butterfly computation unit used in FFT computation is used to compute received signal power, at a timing at which multiplication in a butterfly computation is not used in a final stage of FFT computation, to perform computation of the received signal power simultaneously with FFT computation.</p> |
