| 摘要 |
A display unit includes a display panel and a drive circuit, the display panel including pixels, each pixel including a light emitting element and a pixel circuit, wherein the pixel circuit includes a first transistor being configured to sample a voltage of a signal line, a second transistor being configured to control a current applied to the light emitting element, a third transistor being connected to the source of the second transistor, and a holding capacitor configured to hold the voltage sampled by the first transistor, the drive circuit being configured to, when pixel rows are grouped into units, sequentially perform correction of adjusting a gate-to-source voltage of the second transistor to be close to a threshold voltage of the second transistor for each of the units, being configured to sequentially output a fixed voltage to a source of the second transistor before performing the correction. |
| 主权项 |
1. A display unit comprising: a display panel; and a drive circuit configured to drive the display panel,
the display panel including a plurality of pixels arranged in a matrix, each pixel including a light emitting element and a pixel circuit, a plurality of signal lines, a plurality of scan lines, one or a plurality of first power lines, a plurality of second power lines, and a plurality of control lines, wherein the pixel circuit includes
a first transistor having a gate electrically connected to one of the scan lines and a source or a drain electrically connected to one of the signal lines, and being configured to sample a voltage applied to the signal line,a second transistor having a source or a drain electrically connected to one of the first power lines, and being configured to control a current applied to the light emitting element in accordance with a level of the voltage sampled by the first transistor,a third transistor having a gate, a source, and a drain, the gate of the third transistor being electrically connected to one of the control lines, one of the source and the drain of the third transistor being electrically connected to a terminal of one of the source and the drain of the second transistor, the other of the source and the drain of the third transistor being electrically connected to one of the second power lines, the terminal being unconnected to the one or one of the plurality of first power lines, anda holding capacitor configured to hold the voltage sampled by the first transistor, and wherein the drive circuit includes
a signal line drive circuit configured to continuously output a first fixed voltage to each of the signal lines throughout a first half of one frame period, and then continuously output a signal voltage corresponding to an image signal to each of the signal lines in a second half of the one frame period,a scan line drive circuit configured to, when the plurality of scan lines are grouped into a plurality of first units, sequentially output a first selection pulse for each of the first units to perform correction of adjusting a gate-to-source voltage of the second transistor to be close to a threshold voltage of the second transistor in a first half of one frame period, and then sequentially output a second selection pulse to each of the scan lines to write the signal voltage to the gate of the second transistor in a second half of the one frame period,a control line drive circuit configured to, when the plurality of control lines are grouped into a plurality of second units having a number equal to that of the first units, sequentially output a control pulse for each of the second units to write a second fixed voltage to the terminal before performing the correction, anda power supply circuit configured to continuously output a third fixed voltage and continuously output the second fixed voltage to each of the second power lines in one frame period. |
