| 发明名称 |
SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND PROGRAM |
| 摘要 |
Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates. |
| 申请公布号 |
US2015349947(A1) |
申请公布日期 |
2015.12.03 |
| 申请号 |
US201414759888 |
申请日期 |
2014.01.15 |
| 申请人 |
SONY CORPORATION |
发明人 |
Hirayama Yuichi;Okada Satoshi;Mizutani Yuichi |
| 分类号 |
H04L7/10;H04L7/04 |
主分类号 |
H04L7/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A signal processing device comprising:
a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates. |
| 地址 |
Tokyo JP |
