发明名称 System and Method for Shared Memory for FPGA Based Applications
摘要 A system for shared memory for field programmable gate array based application which includes a host computer, at least one field program gate array and a physical interface is disclosed. The host computer includes a host computer processor, a host computer memory, a shared memory, a host computer interface and a host computer design bus. The host computer design bus is electrically connected to the host computer processor, the host computer memory, the shared memory, and the host computer interface. The field program gate array includes a field program gate array processor, a field program gate array memory, a field program gate array design bus and a field program gate array interface. The field program gate array design bus is electrically connected to the field program gate array processor, the field program gate array interface and the field program gate array memory.
申请公布号 US2015347324(A1) 申请公布日期 2015.12.03
申请号 US201514724864 申请日期 2015.05.29
申请人 S2C INC. 发明人 Tsuji Tomoyuki;Ndzana Ndoua Theodore Lambert
分类号 G06F12/14;G06F13/42;G06F13/16 主分类号 G06F12/14
代理机构 代理人
主权项 1. A system for shared memory for field programmable gate array based application, comprising: a host computer, comprising: a host computer processor;a host computer memory;a shared memory;a host computer interface; anda host computer design bus, electrically connected to the host computer processor, the host computer memory, the shared memory, and the host computer interface; at least one field program gate array, comprising: a field program gate array processor;a field program gate array memory;a field program gate array design bus, electrically connected to the field program gate array processor, and the field program gate array memory; anda field program gate array interface, and comprising: a shared memory controller;a descriptor block;a master interface, used for connecting to the field program gate array design bus; anda host computer connecting physical interface, used for connecting to the host computer interface, and electrically connected to the shared memory controller, the descriptor block and the master interface; and a physical interface, connected to the host computer interface and the host computer connecting physical interface.
地址 San Jose CA US