发明名称 Lifetime mixed level non-volatile memory system
摘要 A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module, The flash controller is farther adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
申请公布号 US9196385(B2) 申请公布日期 2015.11.24
申请号 US201414525411 申请日期 2014.10.28
申请人 Greenthread, LLC 发明人 Rao G. R. Mohan
分类号 G11C29/52;G11C29/00;G06F11/10;G11C11/56 主分类号 G11C29/52
代理机构 Howison & Arnott, LLP 代理人 Howison & Arnott, LLP
主权项 1. A system for storing data comprising: at least one MLC non-volatile memory module comprising a plurality of individually erasable blocks; at least one SLC non-volatile memory module comprising a plurality of individually erasable blocks; and a flash translation layer (FTL); wherein the FTL is adapted to: a) maintain an address map of at least one of the MLC and SLC non-volatile memory modules, the address map comprising a list of logical address ranges accessible by a computer system, the list of logical address ranges having a minimum quanta of addresses, wherein each entry in the list of logical address ranges maps to a similar range of physical addresses within either the at least one SLC non-volatile memory module or within the at least one MLC non-volatile memory module;b) determine if a range of addresses listed by an entry and mapped to a similar range of physical addresses within the at least one MLC non-volatile memory module, fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available equivalent range of physical addresses within the at least one SLC non-volatile memory module;c) determine which of the blocks of the plurality of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; andd) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module.
地址 Dallas TX US