SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE

摘要

According to one embodiment, a first well of the first conductivity type which is formed in a substrate, a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

主权项

1. A semiconductor memory device comprising:
a plurality of memory cells of a first conductivity type; a plurality of select transistors adjacent to one of the plurality of memory cells; a plurality of bit lines connected to one of the plurality of select transistors; a plurality of bit line select transistors of the first conductivity type which connect to one of a plurality of bit lines and a sense amplifier; a first well of the first conductivity type which is formed in a substrate; and a second well of a second conductivity type which is formed in the first well, wherein the plurality of memory cells and the plurality of bit line select transistors are formed in the second well, and wherein in an erase operation, a first voltage which is more than 0V is applied to gates of the plurality of bit line select transistors before an erase voltage is applied to the second well.