Electrically isolated power semiconductor package with optimized layout

摘要

A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

主权项

1. A method of manufacturing a packaged power semiconductor device, comprising:
forming an amount of encapsulant over a semiconductor die, a substrate and a portion of each of a plurality of electrically conductive leads such that the amount of encapsulant does not cover a major surface of the substrate thereby leaving a portion of the substrate exposed on a lower surface of the packaged power semiconductor device, wherein the amount of encapsulant that is formed includes an extended region of encapsulant that extends away from the plurality of electrically conductive leads, wherein the extended region has an upper surface, a lower surface, an end surface opposite the electrically conductive leads, and a pair of side surfaces, wherein a protrusion of encapsulant extends downward from the lower surface of the extended region at a location on the lower surface adjacent to the end surface, and wherein the amount of encapsulant defines a hole that extends from the upper surface of the extended region to the lower surface of the extended region and does not extend through any part of the substrate.