Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks

摘要

An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns.

主权项

1. An integrated circuit, comprising:
an array of memory cells arranged into:
a plurality of rows; anda plurality of main columns coupled to a plurality of bit lines; a set of redundant columns for repairing the array,
wherein the plurality of main columns and the set of redundant columns are divided into row blocks, and a particular one of the row blocks in one of the plurality of main columns is repairable by the particular one of the row blocks in one of the set of redundant columns; status memory coupled to the plurality of bit lines, the status memory indicating repair statuses of the repairs by the set of redundant columns; and control circuitry that, responsive to the integrated circuit receiving a command, performs an update on the status memory with the repair statuses of only a subset of the row blocks of the plurality of main columns.