发明名称 Large interconnect fabrics
摘要 In one embodiment, a network switch includes multiple chips communicably coupled together and a buffered crossbar. Each chip is coupled to every other chip with two bi-directional serial channels and includes a slice of the buffered crossbar. One or more input ports, one or more output ports, and an input logic module are coupled to the plurality of chips, and the input logic module is configured to receive a packet of data, allocate the packet of data into one or more data fragments, and distribute the packet of data to the buffered crossbar. An output logic module is coupled to the chips and configured to retrieve the packet of data from the buffered crossbar, reconstruct the packet of data from the data fragments according to a gather scheme, and transmit the packet of data.
申请公布号 US9160685(B2) 申请公布日期 2015.10.13
申请号 US201213417091 申请日期 2012.03.09
申请人 Cisco Technology, Inc. 发明人 Somasundaram Madian
分类号 H04L12/28;H04L12/935;H04L12/933;H04L12/931 主分类号 H04L12/28
代理机构 Baker Botts L.L.P. 代理人 Baker Botts L.L.P.
主权项 1. A network switch, comprising: a plurality of chips communicably coupled together and comprising a buffered crossbar, each chip coupled to each other chip with two bi-directional serial channels, each chip comprising a slice of the buffered crossbar; one or more input ports; one or more output ports; an input logic module coupled to the plurality of chips, the input logic module configured to: receive a packet of data;allocate the packet of data into a plurality of data fragments, wherein a total number of the plurality of data fragments is dependent on a number of the plurality of chips comprising the buffered crossbar; anddistribute the packet of data to the buffered crossbar, each data fragment being distributed to a particular chip comprising a slice of the buffered crossbar according to a scatter scheme, each of the plurality of chips receiving a selected one of the plurality of data fragments; and an output logic module coupled to the plurality of chips, the output logic module configured to: retrieve the packet of data from the buffered crossbar by retrieving the plurality of data fragments from the plurality of chips;reconstruct the packet of data from the plurality of data fragments according to a gather scheme; andtransmit the packet of data.
地址 San Jose CA US
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