发明名称 |
Looking ahead bytecode stream to generate and update prediction information in branch target buffer for branching from the end of preceding bytecode handler to the beginning of current bytecode handler |
摘要 |
A bytecode interpreter is provided. The interpreter assists in branch prediction by a host processor reducing branch misprediction and achieving high performance. The bytecode branch processor includes an interpreter configured to process a program in a bytecode format in a virtual machine, a branch information generator configured to obtain, while a predefined number of bytecodes are read prior to a current bytecode being processed by the interpreter, a branch address and a target address of a predicted path of a branch corresponding to a preceding bytecode, the branch address being of a branch code included in a preceding handler that processes the preceding bytecode, and the target address being of a current handler that processes the current bytecode to which the preceding handler branches, and a branch target buffer updater configured to update a branch target buffer in the bytecode branch processor with the obtained branch address and target address. |
申请公布号 |
US9158545(B2) |
申请公布日期 |
2015.10.13 |
申请号 |
US201113276083 |
申请日期 |
2011.10.18 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Sihn Kue-Hwan;Cho Seung-Mo |
分类号 |
G06F9/32;G06F9/38;G06F9/455 |
主分类号 |
G06F9/32 |
代理机构 |
NSIP Law |
代理人 |
NSIP Law |
主权项 |
1. A bytecode branch processor, the bytecode branch processor comprising:
an interpreter configured to process a program in a bytecode format in a virtual machine; a branch information generator configured to obtain, while a predefined number of bytecodes are read prior to a current bytecode being processed by the interpreter, a branch address and a target address of a predicted path of a branch corresponding to a preceding bytecode preceding the current bytecode by using a table that comprises a preceding opcode, a length of the preceding bytecode, and the branch address, which are mapped according to the order of bytecode processing, the branch address being of a branch code included in a preceding handler that processes the preceding bytecode, and the target address being of a current handler that processes the current bytecode to which the preceding handler branches; and a branch target buffer (BTB) updater configured to update a branch target buffer (BTB) in the bytecode branch processor with the obtained branch address and target address, wherein the interpreter is further configured to process a branch prediction and to remove a branch misprediction by checking whether the obtained branch address and target address in the BTB is validated in the branch prediction of the current bytecode. |
地址 |
Suwon-si KR |