VIA USING ZN OR ZN ALLOYS AND ITS MAKING METHOD, 3D CHIP STACK PACKAGES USING THEROF

摘要

A via using Zn or Zn alloys and its making method is provided to reduce a processing time by filing a via hole with Zn and Zn alloy. A via hole is formed by performing deep reactive ion etching and a laser drilling to a silicon chip. A seed layer is deposited on the chip through a sputtering and PVD. A planting layer(130) is formed on the seed layer through electroplating and DC electrodeposition. A bubble generated in a processing of Zn or Zn alloy is suppressed by removing an oxide film. A chip for a chip stack process is formed by performing thinning through a CMP(Chemical Mechanical Polishing) of the front and rear of the chip.