| 发明名称 |
System and Method of Clocking an IP Core During a Debugging Operation |
| 摘要 |
According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.
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| 申请公布号 |
US2010313058(A1) |
申请公布日期 |
2010.12.09 |
| 申请号 |
US20100700227 |
申请日期 |
2010.02.04 |
| 申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
BENSINGER GREG;BRAULT JEAN-MARC;MULTHAUP HANS ERICH |
| 分类号 |
G06F1/04;G06F11/36 |
主分类号 |
G06F1/04 |
| 代理机构 |
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| 主权项 |
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| 地址 |
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