发明名称 |
Synchronized charge pump-driven input buffer and method |
摘要 |
An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal. |
申请公布号 |
EP2922207(A1) |
申请公布日期 |
2015.09.23 |
申请号 |
EP20140001075 |
申请日期 |
2014.03.21 |
申请人 |
LINEAR TECHNOLOGY CORPORATION |
发明人 |
MAYES, MICHAEL KEITH;KAPLAN, TODD STUART;BLISS, DAVID EDWARD |
分类号 |
H03M1/08;H03M1/12 |
主分类号 |
H03M1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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