Display

摘要

A display is disclosed. The display comprises a panel, a data driver and a scan driver. The panel comprises pixels, data lines and scan lines. The data lines transmit data signals to the pixels, and the scan lines transmit scan signals to the pixels. The data driver provides the data signals, and the scan driver provides the scan signals. The scan driver comprises a shift register circuit. The shift register circuit comprises an i+1th stage carry shift register, an ith stage carry shift register and a jth stage buffer shift register. The ith stage carry shift register generates an i+1th start signal to start the i+1th stage carry shift register, so that the i+1th stage carry shift register generates an i+2th start signal. The i+1th start signal starts the jth stage buffer shift register to generate a jth output signal.

主权项

1. A display, comprising:
a panel, comprising:
a plurality of pixels;a plurality of data lines for transmitting a plurality of data signals to these pixels;a plurality of scan lines for transmitting a plurality of the scan signals to these pixels; a data driver for providing these data signals; and a scan driver for providing these scan signals, wherein the scan driver comprises:
a shift register circuit, comprising:
a plurality of stages of carry shift registers for generating a plurality of start signals, wherein these start signals comprise an ith start signal and an i+1th start signal, and these stages of carry shift registers comprise:
an ith stage carry shift register for generating the i+1th start signal to start an i+1th stage carry shift register, so that the i+1th stage carry shift register to generate an i+2th start signal; anda plurality of stages of buffer shift registers for generating a plurality of output signals comprising a jth output signal and respectively corresponding to these scan signals, wherein these stages of buffer shift registers comprise:
a jth stage buffer shift register, wherein the i+1th start signal starts the jth stage buffer shift register to generate the jth output signal, wherein the jth output signal and the i+2th start signal are generated from the i+1 start signal, wherein j is equal to i+1.