发明名称 半導体集積回路
摘要 A compound semiconductor integrated circuit chip has a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extend over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.
申请公布号 JP5763704(B2) 申请公布日期 2015.08.12
申请号 JP20130093771 申请日期 2013.04.26
申请人 ウィン セミコンダクターズ コーポレーション 发明人 高谷 信一郎;シャオ シェン・フー;リン チェン・クオ;ファ チャン・ファン
分类号 H01L21/3205;H01L21/331;H01L21/338;H01L21/768;H01L21/822;H01L23/522;H01L25/065;H01L25/07;H01L25/18;H01L27/04;H01L27/095;H01L29/737;H01L29/778;H01L29/812 主分类号 H01L21/3205
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