发明名称 |
Memory system having an encoding processing circuit for redundant encoding process |
摘要 |
In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data. |
申请公布号 |
US9105358(B2) |
申请公布日期 |
2015.08.11 |
申请号 |
US201113157396 |
申请日期 |
2011.06.10 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Tarui Masaya;Kanai Tatsunori;Yamada Yutaka |
分类号 |
G06F11/16;G06F11/10;G11C29/04;G11C29/42;G06F11/08;H03M13/19 |
主分类号 |
G06F11/16 |
代理机构 |
Amin, Turocy & Watson, LLP |
代理人 |
Amin, Turocy & Watson, LLP |
主权项 |
1. A memory system for writing redundant data output by an encoding processing circuit, comprising:
a memory, electrically rewritable by using memory cells capable of having two different resistance values corresponding to logical values of 1 or 0 respectively, the redundant data is read from the memory and a predetermined logical value is written to the memory by flowing current in a same direction; the encoding processing circuit performs redundant encoding processing on target data and outputs redundant data, a number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory; and a decoding circuit that reads data from the memory, and performs a decoding process on the data. |
地址 |
Tokyo JP |