Byte Erasable Non-volatile Memory Architecture And Method Of Erasing Same

摘要

Memory cells arranged in rows and columns, each with source and drain regions of equal breakdown voltages, and floating and control gates over the channel region. The memory cell rows are arranged in clusters each with a source line connecting all the source regions in just that cluster. Word lines each connect all the control gates for a row of memory cells. Bit lines each connect all the drain regions for a column of memory cells. Source line interconnects each connect all the source lines for a column of clusters. One cluster is erased by applying a positive voltage to a word line for that cluster and ground potential to other word lines, ground potential to the source line interconnect for that cluster and a positive voltage to other source line interconnects, and ground potential to the bit lines for that cluster and a positive voltage to other bit lines.

主权项

1. A memory device, comprising:
a plurality of memory cells arranged in rows and columns, wherein each of the memory cells comprises:
spaced apart source and drain regions in a semiconductor substrate with a channel region extending therebetween, wherein the source region and the drain region form junctions with substantially equal breakdown voltages;a floating gate disposed over and insulated from a first portion of the channel region; anda control gate disposed over and insulated from a second portion of the channel region; each row of the memory cells are arranged in clusters of the memory cells with the clusters arranged in rows and columns, wherein each cluster comprises a source line connecting together the source regions of the memory cells in the cluster, wherein each source line is not connected to the source regions of memory cells in other clusters in a same row of clusters; each row of the memory cells comprises a word line connecting together all the control gates of the memory cells in the row of memory cells; each column of the memory cells comprises a bit line connecting together all the drain regions of the memory cells in the column of memory cells; each column of clusters comprises a source line interconnect connecting together all the source lines of the clusters in the column of clusters.