发明名称 AMPLIFIER CIRCUIT
摘要 Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof.
申请公布号 US2015207468(A1) 申请公布日期 2015.07.23
申请号 US201514594773 申请日期 2015.01.12
申请人 Seiko Instruments Inc. 发明人 TOMIOKA Tsutomu
分类号 H03F1/52;H03F3/16 主分类号 H03F1/52
代理机构 代理人
主权项 1. An amplifier circuit configured to amplify a signal input to an input terminal and to output the amplified signal to an output terminal, the amplifier circuit comprising: a first transistor including a gate connected to the input terminal; a second transistor including a drain connected to the output terminal and a source connected to a drain of the first transistor, the second transistor having a drain breakdown voltage higher than a drain breakdown voltage of the first transistor and being always in an operating state; and a clamp circuit connected to the drain of the first transistor, and configured to limit a drain voltage of the first transistor.
地址 Chiba-shi JP