发明名称 Methods and systems for routing an electronic design using spacetiles
摘要 Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punches for the muting layer, identify an area probe from the spacetiles, and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punches to form spacetiles for the routing layers, determine a via spacetile layer, identify spacetiles as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two muting layers. One of the two routing layers may be a tracked muting layer, and the other may be a trackless routing layer. The tracked muting may be gridded or gridless.
申请公布号 US9075932(B1) 申请公布日期 2015.07.07
申请号 US201213602069 申请日期 2012.08.31
申请人 Candence Design Systems, Inc. 发明人 Salowe Jeffrey S.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Vista IP Law Group, LLP 代理人 Vista IP Law Group, LLP
主权项 1. A computer implemented method for routing an electronic design using one or more spacetiles, comprising: identifying a first routing layer of an electronic design and one or more spacetiles of the first routing layer, in which the first routing layer is gridded and is associated with at least two sets of tracks in two routing directions; identifying a second routing layer of the electronic design, in which the second routing layer is gridless; identifying or determining a via spacetile layer based at least in part upon the one or more spacetiles for the first routing layer and the second routing layer of the electronic design; and routing the electronic design while transitioning between the first routing layer and the second routing layer by using the via spacetile layer.
地址 San Jose CA US