MIXED SIZE DATA PROCESSING OPERATION

摘要

A data processing system includes a processor core and a memory. The processor core includes processing circuitry controlled by control signals generated by decoder circuitry which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.

主权项

1. Apparatus for processing data comprising:
processing circuitry configured to perform data processing operations specified by program instructions; a plurality of registers, each of said registers storing a scalar operand; and decoder circuitry coupled to said processing circuitry and configured to decode said program instructions to generate control signals for controlling said processing circuitry to perform data processing operations specified by said program instructions; wherein said decoder circuitry is configured to decode a mixed operand size arithmetic instruction to generate control signals to control said processing circuitry to perform a mixed size data processing operation having:
(i) a first input operand of a first operand size stored within a first register of said plurality of registers as specified by a first register specifying field within said mixed operand size arithmetic instruction;(ii) a second input operand of a second operand size stored within a second register of said plurality of registers as specified by a second register specifying field within said mixed operand size arithmetic instruction, said second operand size being less than said first operand size; and(iii) a third operand of a third operand size, a parameter field within said mixed operand size arithmetic instruction indicates an operand size of the second input operand and whether the second input operand is to be zero extended or sign extended; and said mixed size data processing operation including processing with a same effect as:
(a) converting said second input operand from said second operand size to said first operand size in dependence on said parameter field; and(b) generating said third operand in dependence upon said first input operand with said first operand size and said second input operand with said first operand size.