METHOD AND SYSTEM OF VERIFYING PROPER EXECUTION OF A SECURE MODE ENTRY SEQUENCE

摘要

A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.

主权项

1. A method comprising:
delivering an instruction from a memory to a processor across an instruction bus, the instruction at least partially configuring the processor for a secure mode of operation different than privilege modes of the processor; checking for a proper sequence of signals in the instruction, said checking being performed external to said processor; and allowing entry into the secure mode of operation in response to the proper sequence of signals in the instruction.