CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS

摘要

A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

主权项

1. A method of characterizing block mask overlay tolerance of an integrated circuit design, said method comprising the steps of:
obtaining a physical test integrated circuit having a plurality of repeating circuit portions corresponding to said integrated circuit design, a first of said portions being fabricated with a nominal block mask location, additional ones of said portions being deliberately fabricated with predetermined progressive increased offset of said block mask location from said nominal block mask location; for each of said portions, determining a difference in threshold voltage between a first field effect transistor and a second field effect transistor, wherein said predetermined progressive increased offset of said block mask location is in a direction from said first field effect transistor to said second field effect transistor; and determining said block mask overlay tolerance at a value of said progressive increased offset corresponding to an inflection of said difference in threshold voltage from a zero difference; wherein said obtaining step comprises fabricating said physical test integrated circuit; wherein said integrated circuit design comprises a static random access memory and wherein said fabricating comprises fabricating said repeating circuit portions as test static random access memory cells; and wherein in said step of determining said difference in threshold voltage between said first field effect transistor and said second field effect transistor, said first field effect transistor comprises one of a left-hand pull-up transistor and a right-hand pull-up transistor, and said second field effect transistor comprises another one of said left-hand pull-up transistor and said right-hand pull-up transistor.