VECTOR PROCESSING ENGINES (VPEs) EMPLOYING REORDERING CIRCUITRY IN DATA FLOW PATHS BETWEEN EXECUTION UNITS AND VECTOR DATA MEMORY TO PROVIDE IN-FLIGHT REORDERING OF OUTPUT VECTOR DATA STORED TO VECTOR DATA MEMORY, AND RELATED VECTOR PROCESSOR SYSTEMS AND METHODS

摘要

Vector processing engines (VPEs) employing reordering circuitry in data flow paths between execution units and vector data memory to provide in-flight reordering of output vector data stored to vector data memory are disclosed. Related vector processor systems and methods are also disclosed. Reordering circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The reordering circuitry is configured to reorder output vector data sample sets from execution units as a result of performing vector processing operations in-flight while the output vector data sample sets are being provided over the data flow paths from the execution units to the vector data memory to be stored. In this manner, the output vector data sample sets are stored in the reordered format in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in the execution units.

主权项

1. A vector processing engine (VPE) configured to in-flight reorder a resultant output vector data sample set generated by at least one execution unit executing a vector processing operation, comprising:
at least one vector data file configured to:
provide a fetched input vector data sample set in at least one input data flow path for a vector processing operation; andreceive a reordered resultant output vector data sample set from at least one output data flow path to be stored; at least one execution unit provided in the at least one input data flow path, the at least one execution unit configured to:
receive the input vector data sample set; andexecute the vector processing operation on the input vector data sample set to provide a resultant output vector data sample set on the at least one output data flow path; and at least one reordering circuitry configured to:
receive the resultant output vector data sample set on the at least one output data flow path;reorder the resultant output vector data sample set into the reordered resultant output vector data sample set without the resultant output vector data sample set being stored in the at least one vector data file; andprovide the reordered resultant output vector data sample set on the at least one output data flow path.