发明名称 |
MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING |
摘要 |
A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. |
申请公布号 |
WO2015066704(A1) |
申请公布日期 |
2015.05.07 |
申请号 |
WO2014US63912 |
申请日期 |
2014.11.04 |
申请人 |
MARVELL WORLD TRADE, LTD. |
发明人 |
SIGNOFF, DAVID, M.;HE, MING;LOEB, WAYNE, A. |
分类号 |
H03F1/32;H03F1/30 |
主分类号 |
H03F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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