| 摘要 |
A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers. |
| 主权项 |
1. An image sensor using backside illumination photodiodes, comprising:
a plurality of first metal layers formed in a first wafer including a plurality of backside illumination photodiodes which sense light incident from a backside and output signals and a plurality of transfer transistors which transfer the signals outputted from the backside illumination photodiodes, to floating diffusion nodes, the plurality of first metal layers being electrically connected with the floating diffusion nodes, respectively; a plurality of second metal layers formed in a second wafer including a plurality of pixel transistors which process signals transferred through the floating diffusion nodes and transfer processed signals, the plurality of second metal layers being electrically connected with the pixel transistors, respectively; a plurality of first bonding vias formed in the first wafer, and having one ends which are electrically connected to the first metal layers, respectively; a plurality of second bonding vias formed in the second wafer, and having one ends which are electrically connected to the second metal layers, respectively; and a plurality of bonding pads formed in the first wafer, and having one ends which are electrically connected with the other ends, respectively, of the first bonding vias and the other ends which are electrically connected with the other ends, respectively, of the second bonding vias. |
