| 摘要 |
<p>The present invention relates to a single channel asynchronous bridge system for interconnecting blocks of different domains in system on chip (SoC) which has multiple domains. In detail, the present invention relates to a single channel asynchronous bridge system which links the blocks to a single payload channel in the asynchronous bridge regardless of FIFO depth to make block connection simple and to reduce chip size and time for making chip design; improves full system performance through FIFO depth setting by the bus performance transmitting payload data between blocks; minimizes the data time limitation by transmitting transmitter domain clerk to a receiver to make the design easy; and prevents multibit CDC problems by using a single bit control signal between a transmitter and the receiver.</p> |
