Avoiding BIST and MBIST intrusion logic in critical timing paths

摘要

Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.

主权项

1. An apparatus comprising:
a plurality of scan cells connected into one or more scan chains, wherein a scan data input of at least one scan cell is configured to receive built-in test data during BIST testing and scan test data during scan testing; at least one execution unit having at least one multi-cycle ALU, at least one single-cycle ALU, at least one physical register file (PRF), and a multiplexer configured to couple test data onto the result path of the multi-cycle ALU and wherein the test data is written into the PRF by executing an operation in one of the ALUs.