主权项 |
1. A display apparatus comprising:
a display panel having a plurality of first pixels and a plurality of second pixels, wherein the first pixels are disposed in a frame display region of the display panel, the second pixels are disposed in an extending display region of the display panel, and the extending display region surrounds the frame display region; a timing controller receiving a frame data corresponding to a display frame and outputting a plurality of display data correspondingly; a data driving unit coupled to the first pixels and the timing controller so as to receive the display data, and providing a plurality of first driving signals to the first pixels according to the display data; an extending driving unit coupled to the second pixels and the data driving unit and receiving a display reference data corresponding to the display frame through the data driving unit, and the extending driving unit provides a second driving signal to the second pixels according to the display reference data so as to determine a display effect of the second pixels; and a power supply unit coupled to the display panel for providing a common voltage to the display panel, wherein the common voltage is adjusted corresponding to a feed-through voltage of the first pixels, wherein the extending driving unit comprises:
a level-adjusting circuit for receiving a display reference signal corresponding to the display reference data and adjusting the display reference signal so as to generate the second driving signal according to the feed-through voltage, wherein the level-adjusting circuit comprises:
a first operational amplifier having a first input end, a second input end and a first output end, wherein the first output end outputs the second driving signal;a first resistor coupled between the display reference signal and the first input end;a second resistor coupled between the common voltage and the first input end;a third resistor coupled between a ground voltage and the second input end; anda fourth resistor, coupled between the second input end and the first output end. |