NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING FOR STATIC RANDOM ACCESS MEMORY (SRAM)

摘要

In one embodiment, one portion of an SRAM array is stressed by first writing a “1” in every bit of the array, followed by an evaluation of the relevant parameters of the array using a ring oscillator driven by a mirrored bit-line current, the ring oscillator not in line of the bit-line of the SRAM. The other portion of the array is then stressed after writing a “0” in every bit of the array. The evaluation procedure is then repeated.

主权项

1. A method of evaluating negative bias thermal instability stress test effects on a static random-access memory (SRAM) comprising:
characterizing an unstressed SRAM array; stressing the SRAM array by elevating a source-gate voltage for a subset of P-devices in the SRAM array whose gates are at zero to a stress level; releasing the stressing; and characterizing the SRAM array using a ring oscillator coupled to a mirrored bit-line current, the output of the ring oscillator representing a threshold voltage and saturation current of the SRAM array after stressing.