Memory interface device and methods thereof

摘要

A data processing device includes a load/store module to provide an interface between a processor device and a bus. In response to receiving a load or store instruction from the processor device, the load/store module determines a predicted coherency state of a cache line associated with the load or store instruction. Based on the predicted coherency state, the load/store module selects a bus transaction and communicates it to the bus. By selecting the bus transaction based on the predicted cache state, the load/store module does not have to wait for all pending bus transactions to be serviced, providing for greater predictability as to when bus transactions will be communicated to the bus, and allowing the bus behavior to be more easily simulated.

主权项

1. A method comprising:
receiving a first memory request associated with a first address; in response to receiving the first memory request, determining, via a control module within a load/store module, a first predicted coherency state of a first cache location associated with the first address by selecting the first predicted coherency state from a plurality of possible states based on a type of a first pending bus transaction associated with the first address, the first pending bus transaction resulting from a second memory request received prior to the first memory request, the type of the first pending bus transaction selected from the group consisting of a load transaction and a store transaction; determining, via the control module, a first bus transaction based on the first predicted coherency state; and communicating the first bus transaction.