发明名称 MEMORY SYSTEM FOR SHADOWING VOLATILE DATA
摘要 An apparatus configured to shadow volatile data while minimizing read latency is described. In an implementation, the apparatus includes a memory controller configured to operatively couple to a volatile memory device and a non-volatile memory device. The volatile memory device includes a volatile memory cell and the non-volatile memory device includes a corresponding non-volatile memory cell. The volatile memory device has a first transfer speed and the non-volatile memory device has a second transfer speed. The memory controller is configured to cause storage of data to the volatile memory cell and the non-volatile memory cell and to determine an occurrence of an unanticipated power outage. The memory controller is configured set a read speed to the second transfer speed and to cause replication of the data from the non-volatile memory cell to a corresponding volatile memory cell upon recovery from the unanticipated power outage.
申请公布号 US2015019795(A1) 申请公布日期 2015.01.15
申请号 US201314043190 申请日期 2013.10.01
申请人 LSI Corporation 发明人 McCollum Justin R.;Stuhlsatz Jason M.;Abraham Moby J.
分类号 G11C14/00;G06F12/02 主分类号 G11C14/00
代理机构 代理人
主权项 1. An apparatus comprising: a memory controller configured to operatively couple to a volatile memory device and a non-volatile memory device, the volatile memory device having a first transfer speed and the non-volatile memory device having a second transfer speed, the volatile memory device including at least one volatile memory cell and the non-volatile memory device including at least one non-volatile memory cell, the at least one non-volatile memory cell corresponding to the at least one volatile memory cell, the memory controller configured to cause storage of data to the at least one volatile memory cell and the at least one non-volatile memory cell; determine an occurrence of an unanticipated power outage; set a read speed to the second transfer speed; and cause replication of the data from the at least one non-volatile memory cell to the at least one volatile memory cell.
地址 San Jose CA US
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