发明名称 |
Solid-state imaging device |
摘要 |
According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer. |
申请公布号 |
US8916917(B2) |
申请公布日期 |
2014.12.23 |
申请号 |
US201213365627 |
申请日期 |
2012.02.03 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Furuya Shogo;Yamashita Hirofumi;Yamaguchi Tetsuya |
分类号 |
H01L31/101;H01L27/146 |
主分类号 |
H01L31/101 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A solid-state imaging device comprising:
a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first surface and a second surface opposite to the first surface; an upper element isolation layer provided on the first surface in the element isolation region; a lower element isolation layer provided between the second surface and the upper element isolation layer; a first photodiode comprising a first impurity layer provided in the element formation region; a floating diffusion provided in the element formation region; and a first transistor disposed between the first photodiode and the floating diffusion and comprising a first gate electrode provided on the first surface, wherein in a direction level with the first surface of the semiconductor substrate, a side surface of the lower element isolation layer facing the transistor across the first impurity layer protrudes closer to the transistor than a side surface of the upper element isolation layer located on the lower element isolation layer, the upper element isolation layer and the lower element isolation layer are impurity layers, and a concentration of the impurity layer as the lower element isolation layer is less than or equal to a concentration of the impurity layer as the upper element isolation layer wherein the upper element isolation layer has the same width as that of the lower element isolation layer. |
地址 |
Tokyo JP |