SHIELDED VERTICALLY STACKED DATA LINE ARCHITECTURE FOR MEMORY

摘要

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

主权项

1. An apparatus comprising:
a first string of vertically stacked memory cells; a first plurality of vertically stacked data lines, wherein a data line of the first plurality of data lines is coupled to the first string of memory cells through a first select device; a second string of vertically stacked memory cells; and a second plurality of vertically stacked data lines, wherein a data line of the second plurality of data lines is coupled to the second string of memory cells through a second select device and is adjacent to the data line coupled to the first string of memory cells, wherein the apparatus is configured to couple the data line coupled to the first string of memory cells to a shield potential during at least a portion of a memory operation involving a memory cell of the second string of memory cells.