发明名称 Method of fabricating semiconductor device
摘要 A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.
申请公布号 US8912065(B2) 申请公布日期 2014.12.16
申请号 US201213523912 申请日期 2012.06.15
申请人 Nanya Technology Corporation 发明人 Wu Tieh-Chiang;Liao Wei-Ming;Huang Jei-Cheng;Nieh Shin-Yu
分类号 H01L21/336 主分类号 H01L21/336
代理机构 Jianq Chyun IP Office 代理人 Jianq Chyun IP Office
主权项 1. A method for fabricating a semiconductor device, comprising: providing a substrate that has a first area and a second area; forming, over the substrate, a first patterned mask layer that has at least one first opening in the first area and has a plurality of second openings in the second area, wherein the first opening is smaller than the second openings; removing a portion of the substrate, with the first patterned mask layer as a mask, to form at least one first trench in the substrate in the first area and form a plurality of second trenches in the substrate in the second area, wherein a width of the first trench is less than a width of the second trenches, and a depth of the first trench is less than a depth of the second trenches; removing the first patterned mask layer; forming a first dielectric layer at least in the first trench and the second trenches; and forming a conductor structure on the first dielectric layer on at least a portion of a sidewall of the first trench and on the first dielectric layer on at least a portion of a sidewall of the second trenches, wherein the first area comprises a transistor device area, and the second area comprises a capacitor area.
地址 Taoyuan TW