发明名称 メモリシステム及びメモリインターフェース装置
摘要 <p>A memory access source (3) regards a plurality of memory circuits (DIMM 0, 1) as single memory circuit and transmits a row address and a column address in time division to an access control circuit (20). The access control circuit (20) performs a speculative access to the plurality of memory circuits (DIMM 0, 1) when receiving the row address, and performs an access to a memory circuit which is specified by the column address after receiving the column address and sends a cancel command of the speculative access to the other memory circuit out of target. Or, in the case of read access, the access control circuit (20) receives read data from the plurality of memory circuits and discards the read data of the memory circuit out of the target by the column address.</p>
申请公布号 JP5633562(B2) 申请公布日期 2014.12.03
申请号 JP20120517052 申请日期 2010.05.27
申请人 发明人
分类号 G06F12/02;G06F12/06 主分类号 G06F12/02
代理机构 代理人
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