| 发明名称 |
SEMICONDUCTOR TEST METHOD AND SEMICONDUCTOR TEST APPARATUS |
| 摘要 |
A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips. |
| 申请公布号 |
US2014342475(A1) |
申请公布日期 |
2014.11.20 |
| 申请号 |
US201414194400 |
申请日期 |
2014.02.28 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MIKI Kenichi;MORINO Keiji |
| 分类号 |
H01L21/66;H01L21/67;G01R31/26;H01L21/78 |
主分类号 |
H01L21/66 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor test method comprising:
attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips; dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips; and after said dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips. |
| 地址 |
Tokyo JP |
