发明名称 METHOD OF MAKING A DYNAMIC RANDOM ACCESS MEMORY ARRAY
摘要 The present invention is related to microelectronic technologies, and discloses specifically a method of making a dynamic random access memory (DRAM) array. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices.
申请公布号 US2014342516(A1) 申请公布日期 2014.11.20
申请号 US201414264048 申请日期 2014.04.28
申请人 Fudan University 发明人 Dongping Wu;Shi-Li Zhang;Pengfei Wang;Wei Zhang
分类号 H01L27/108 主分类号 H01L27/108
代理机构 代理人
主权项 1. A method of making a DRAM array, the method comprising: forming, for each of a plurality of vertical MOS field-effect-transistor array devices, a first highly doped region near a surface of a semiconductor substrate; etching the semiconductor substrate to form openings; covering sidewalls of the openings with an insulating film; implanting dopant ions into the openings and activating the dopant ions to form second highly doped regions near bottoms of the openings; depositing a first metal layer over the semiconductor substrate, the first metal layer covering the sidewalls and bottoms of the openings; causing the first metal layer to react with the semiconductor substrate near bottoms of the openings to form metal silicide in the second highly doped regions, whereby metal silicide in each opening expands to join metal silicide in neighboring openings to form contiguous bit lines connecting respective sets of multiple consecutive vertical MOS field-effect-transistor array devices; and forming, for the each of the plurality of vertical MOS field-effect-transistor array devices, buried metal double gate structures, the buried metal double gate structures acting as word lines for the DRAM array.
地址 Shanghai CN