Clock and data recovery using LC voltage controlled oscillator and delay locked loop,申请号US201314058506-传众专利搜索

发明名称	Clock and data recovery using LC voltage controlled oscillator and delay locked loop
摘要	A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.
申请公布号	US8885787(B2)	申请公布日期	2014.11.11
申请号	US201314058506	申请日期	2013.10.21
申请人	Taiwan Semiconductor Manufacturing Company, Ltd.	发明人	Chern Chan-Hong;Lin Chih-Chang;Huang Ming-Chieh;Hsueh Fu-Lung
分类号	H04L7/00;H04L7/033;H03L7/08;H03L7/081;H03L7/113	主分类号	H04L7/00
代理机构	Lowe Hauptman & Ham, LLP	代理人	Lowe Hauptman & Ham, LLP
主权项	1. A clock and data recovery (CDR) circuit, comprising: an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency; a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases; a first charge pump configured to control the LCVCO; and a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases.
地址	TW