发明名称 |
Pre-charge tracking of global read lines in high speed SRAM |
摘要 |
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle. A dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the SRAM forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle. |
申请公布号 |
US8879303(B2) |
申请公布日期 |
2014.11.04 |
申请号 |
US201313733578 |
申请日期 |
2013.01.03 |
申请人 |
LSI Corporation |
发明人 |
Chandwani Kamal;Vikash ;Sahu Rahul |
分类号 |
G11C11/00;G11C7/00;G11C7/02;G11C8/00;G11C7/12;G11C11/419 |
主分类号 |
G11C11/00 |
代理机构 |
Sheridan Ross P.C. |
代理人 |
Sheridan Ross P.C. |
主权项 |
1. A memory circuit, comprising:
a static random access memory including N banks of memory cells, each bank having M columns, where M and N are positive integers; rows of M sense amplifiers, each row of the M sense amplifiers placed between two banks of the memory cells, each row of the M sense amplifiers coupled to a sense amplifier control circuit and a local input/output circuit, each column of the M sense amplifiers corresponding to a bit of the memory cell, the bit having corresponding global read lines; a global read precharge tracking control circuit controlling a precharge of the global read lines using a track dummy global read line signal; a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits; and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output tracking circuit and performing a fixed delay tracking of a read operation in a read cycle; wherein a dummy global read line is coupled to the global read precharge tracking control circuit and returns from a half way to the top of the static random access memory forming a tracking dummy global read line that determines a completion of the precharge of the global read lines before the sense amplifiers start discharging the global read lines in the read cycle. |
地址 |
Milpitas CA US |