Verification and debugging using heterogeneous simulation models

摘要

A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

主权项

1. A method of verifying and debugging a module of a circuit design, the module including two or more sub-modules, the method comprising:
inputting test vectors for the module; simulating on a programmed processor, the module of the circuit design on different simulation models including at least a first simulation model, a second simulation model and a third simulation model of the module, the simulating using the test vectors for input to the module and the module being simulated separately from other modules of the circuit design; wherein the first simulation model is an RTL simulation model, the second simulation model is a post-synthesis simulation model, and the third simulation model is a hardware-in-the-loop simulation model; comparing output from the simulation of the module using the first simulation model, output from the simulation of the module using the second simulation model and output from the simulation of the module using the third simulation model; and in response to a discrepancy between outputs from simulation of the second and third simulation models and no discrepancy between outputs from simulation of the first and second simulation models, storing data indicative of an error in the module and, for each sub-module of the two or more sub-modules contained within the module, using the sub-module as the module repeating the inputting test vectors for the module, simulating the module using only the second and third simulation models, comparing output from simulating only the second and third simulation models, and storing data indicative of results of the comparing.