Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

摘要

A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

主权项

1. A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate; a PFET device having an N-well at the top side of the substrate; a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device; and a dopant out-diffused from surfaces of a via opening of the through wafer via into the substrate and a deep well, wherein the substrate contact is arranged to prevent formation of a parasitic circuit.