发明名称 |
Solid-state imaging device with multiplexed read-out and shutter states |
摘要 |
According to one embodiment, a vertical selection circuit that sets an electronic shutter state and a read-out state in time division multiplexing for each selected row of a pixel array unit in which the pixels are arranged in a matrix pattern, a pulse selector circuit that drives the pixels belonging to the selected row in accordance with the electronic shutter state and the read-out state, and a timing generator circuit that controls operational timing of the vertical selection circuit and the pulse selector circuit are included. |
申请公布号 |
US8853609(B2) |
申请公布日期 |
2014.10.07 |
申请号 |
US201213419638 |
申请日期 |
2012.03.14 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Mihara Takahiko;Morisaki Motohiro |
分类号 |
H04N5/353;H04N5/376;H04N5/374 |
主分类号 |
H04N5/353 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A solid-state imaging device comprising:
a pixel array unit in which pixels storing electric charge acquired through a photoelectric conversion are arranged in a matrix pattern; a vertical signal line that transmits pixel signals read out from the pixels in a vertical direction; a vertical selection circuit that sets an electronic shutter state and a read-out state for each selected row of the pixel array unit in time division multiplex; a pulse selector circuit that drives the pixels belonging to the selected row in accordance with the electronic shutter state and the read-out state; and a timing generator circuit that controls operational timing of the vertical selection circuit and the pulse selector circuit, wherein the vertical selection circuit includes: a comparator that is used commonly in the electronic shutter state and the read-out state and compares a row selection value and a row number; and a register that is used commonly in the electronic shutter state and the read-out state and holds a comparison result of the comparator, and wherein the vertical selection circuit performs time division multiplexing of a period in which the electronic shutter state is set and a period in which the read-out state is set. |
地址 |
Tokyo JP |