| 主权项 |
1. A semiconductor chip, comprising:
a region including at least nine linear-shaped conductive structures within a gate electrode level of the semiconductor chip, the at least nine linear-shaped conductive structures oriented to extend lengthwise in a first direction, each of the at least nine linear-shaped conductive structures positioned adjacent to another of the at least nine linear-shaped conductive structures in a second direction perpendicular to the first direction, each of the at least nine linear-shaped conductive structures having a corresponding lengthwise centerline oriented in the first direction, the at least nine linear-shaped conductive structures positioned such that lengthwise centerlines of adjacently positioned ones of the at least nine-linear-shaped conductive structures are separated from each other by a first pitch, the first pitch being a distance measured in the second direction that is less than 193 nanometers, each of the at least nine linear-shaped conductive structures having a corresponding width as measured in the second direction that is less than 193 nanometers, each of the at least nine linear-shaped conductive structures having a corresponding co-planar top surface, the region including a collection of transistors of a first transistor type and a collection of transistors of a second transistor type, the collection of transistors of the first transistor type separated from the collection of transistors of the second transistor type by an inner region that does not include a source or a drain of any transistor, the collection of transistors of the first transistor type including a first transistor of the first transistor type, a second transistor of the first transistor type, a third transistor of the first transistor type, and a fourth transistor of the first transistor type, the collection of transistors of the second transistor type including a first transistor of the second transistor type, a second transistor of the second transistor type, a third transistor of the second transistor type, and a fourth transistor of the second transistor type, the first, second, third, and fourth transistors of the first transistor type and the first, second, third, and fourth transistor of the second transistor type forming a portion of a digital logic circuit, the at least nine linear-shaped conductive structures including a first linear-shaped conductive structure that fauns a gate electrode of the first transistor of the first transistor type, wherein any transistor having its gate electrode formed by the first linear-shaped conductive structure is of the first transistor type, the at least nine linear-shaped conductive structures including a second linear-shaped conductive structure that forms a gate electrode of the first transistor of the second transistor type, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the second transistor type, the at least nine linear-shaped conductive structures including a third linear-shaped conductive structure that foams a gate electrode of the fourth transistor of the first transistor type, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the first transistor type, the at least nine linear-shaped conductive structures including a fourth linear-shaped conductive structure that forms a gate electrode of the fourth transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fourth linear-shaped conductive structure is of the second transistor type, the lengthwise centerline of the first linear-shaped conductive structure substantially aligned with the lengthwise centerline of the second linear-shaped conductive structure such that the lengthwise centerlines of the first and second linear-shaped conductive structures are positioned on a substantially same line of extent in the first direction, the lengthwise centerline of the third linear-shaped conductive structure substantially aligned with the lengthwise centerline of the fourth linear-shaped conductive structure such that the lengthwise centerlines of the third and fourth linear-shaped conductive structures are positioned on a substantially same line of extent in the first direction, the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the fourth transistor of the second transistor type, the gate electrode of the second transistor of the first transistor type electrically connected to the gate electrode of the second transistor of the second transistor type, the gate electrode of the third transistor of the first transistor type electrically connected to the gate electrode of the third transistor of the second transistor type, the gate electrode of the fourth transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type, the gate electrodes of both the second and third transistors of the first transistor type located between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, the gate electrodes of both the second and third transistors of the second transistor type located between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction, the second transistor of the first transistor type having a first diffusion terminal physically and electrically connected to a first diffusion terminal of the third transistor of the first transistor type, the first diffusion terminal of the second transistor of the first transistor type electrically connected to a common node, the first diffusion terminal of the third transistor of the first transistor type electrically connected to the common node, the second transistor of the second transistor type having a first diffusion terminal physically and electrically connected to a first diffusion terminal of the third transistor of the second transistor type, the first diffusion terminal of the second transistor of the second transistor type electrically connected to the common node, the first diffusion terminal of the third transistor of the second transistor type electrically connected to the common node, the second transistor of the first transistor type having a second diffusion terminal electrically connected to a first diffusion terminal of the first transistor of the first transistor type, the second transistor of the second transistor type having a second diffusion terminal electrically connected to a first diffusion terminal of the first transistor of the second transistor type, the third transistor of the first transistor type having a second diffusion terminal electrically connected to a first diffusion terminal of the fourth transistor of the first transistor type, the third transistor of the second transistor type having a second diffusion terminal electrically connected to a first diffusion terminal of the fourth transistor of the second transistor type, the first linear-shaped conductive structure including an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the first linear-shaped conductive structure being the only portion of the first linear-shaped conductive structure above a substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, the second linear-shaped conductive structure including an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the second linear-shaped conductive structure being the only portion of the second linear-shaped conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, the third linear-shaped conductive structure including an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the third linear-shaped conductive structure being the only portion of the third linear-shaped conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, the fourth linear-shaped conductive structure including an electrical connection area in physical connection with another conductive structure of the digital logic circuit, the electrical connection area of the fourth linear-shaped conductive structure being the only portion of the fourth linear-shaped conductive structure above the substrate of the semiconductor chip that is in physical connection with another conductive structure of the digital logic circuit, at least two of the electrical connection areas of the first, second, third, and fourth linear-shaped conductive structures located within the inner region. |
